1. Field of the Invention
The present invention relates generally to a level detecting circuit. More particularly, the invention relates to a negative voltage level detecting circuit to be used for writing operation or erasure operation for a flash memory.
2. Description of the Related Art
In writing operation or erasure operation for a flash memory as a non-volatile memory, it is becoming a trend to use a negative voltage in combination with a positive voltage in order to realize operation at low potential. In a transformer circuit for generating the negative voltage to be used for such purpose, it is important to stably control the output voltage thereof in a wide power source voltage range.
One example of the conventional negative voltage level detecting circuit to be used for such control has been disclosed in Japanese Unexamined Patent Publication No. Heisei 6-68690. Such a circuit will be briefly discussed with reference to FIGS. 4A and 4B.
In FIG. 4A, a level detecting circuit 10 is constructed with a level shifter 1 for inputting a voltage Vn from a negative voltage generating circuit, and a signal amplifier portion 2 for switching a voltage level at a node N0 depending upon an output of the level shifter 1.
The level shifter 1 shown in FIG. 4A is constructed with including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) TN2, p-MOSFET TP2 and p-MOSFET TP3.
On the other hand, the signal amplifier portion 2 is constructed with p-MOSFET TP1 and n-MOSFET N1. The signal amplifier portion 2 receives the output of the level shifter 1 and detects that the voltage Vn is lowered in order to be lower than a desired voltage level Vx (namely, voltage Vn.ltoreq.Vx) (time tx) to switch the voltage at the node N0 from a high level (substantially equal value to a power source voltage Vcc) of a binary signal to a low level (approximately 0V).
The voltage appearing at the node N0 is normally input to a logic gate such as an inverter INV or the like for wave shaping and is transformed into a complete CMOS (Complementary Metal Oxide Semiconductor) logic level signal. This logic level signal is illustrated as signal OUT in FIG. 4B.
On the other hand, in FIG. 4B, when the voltage Vn&gt;Vx, a drain-source voltage of the n-MOSFET TN2 becomes sufficiently high to turn ON the n-MOSFET TN1, ON-resistance of the p-MOSFET TP1 becomes smaller than ON-resistance of the n-MOSFET N1. Therefore, the voltage of the node N0 becomes high level (signal OUT is GND level). On the other hand, when voltage Vn.ltoreq.Vx is established, the drain-source voltage of the n-MOSFET TN2 becomes sufficiently high to turn ON the n-MOSFET TN1, ON-resistance of the n-MOSFET TN1 becomes smaller than ON-resistance of the p-MOSFET TP1. Therefore, the voltage of the node N0 becomes low level (signal OUT is the power source voltage Vcc level).
In the foregoing circuit, voltage level detection (detection signal generation) is performed with ON-resistance ratio of the n-type MOSFET and the p-type MOSFET, and a voltage amplification degree of the signal amplifier portion 2 is low. Therefore, output (voltage at the node N0) inverting operation of the signal amplifier portion 2 is slow to slow-down the operation speed. On the other hand, a problem is encountered in that an inverting period (tx) significantly depends on fluctuation of the power source voltage or device characteristics.
It should be noted that Japanese Unexamined Patent Publication No. Heisei 5-175801 also discloses a circuit including the level shifter and the signal amplifier portion. However, in the circuit disclosed in the above-identified publication, it concerns the power source voltage level (positive voltage) to be supplied to a memory chip. The foregoing drawback is directed to a problem in that the voltage level (negative voltage) generated within the memory chip by the transformer circuit. Accordingly, in the content of disclosure of the above-identified publication, the foregoing problem cannot be solved.